With the advances in the SoC (System on Chip) designs and the continuously increasing complexity and speed of the digital parts in such designs, the task for the synchronization of data paths and the sampling clock is becoming more challenging. Not less important is also the necessity of synthesizing clock signals having frequencies significantly higher than the frequency of a stable external reference clock.
All of these applications require the use of a PLL (Phase Lock Loop), which can be easily integrated in current digital CMOS processes. The VCO (Voltage Controlled Oscillator) for such PLLs can be implemented in the most straightforward manner using ring-oscillators. Ring-oscillators are composed of delay cells connected in a ring and in this case the frequency of oscillation is described by the formula:
                              F          osc                =                  1                      2            ⁢                                                  ⁢                          NT              del                                                          (                  Equation          ⁢                                          ⁢          1                )            
where
N—the number of delay cells in the ring
Tdel—input-output delay of each cell
Due to the high switching activity in the modern designs, there is a lot of noise coupled in the PLL's VCO through the substrate of the chip and from the supply rails. This is why the design of the delay cell should be immune towards these noise sources. Usually, delay cells employ a fully differential architecture. One such prior art differential delay cell 10 is shown in FIG. 1. The differential delay cell 10 is implemented using PMOS transistors 14 and 15. Inputs IN1 and IN2 are connected to the gates of the PMOS transistors 14 and 15, respectively. The drains of the PMOS transistors 14 and 15 are connected to a pair of resistive loads 17 comprising resistors 19 and 18, respectively. The sources of transistors 14 and 15 are connected together with one terminal 12 of a bias current source 11.
The differential delay cell 10 distributes the current of the bias current source 11 between the resistors 18 and 19 proportionally to the voltage difference at the inputs IN1 and IN2. Ideally, the output impedance of the bias current source 11 is high. This isolates the differential delay cell 10 from noise present on the power supply rail SUPL. The noise from substrate and ground is coupled equally to outputs OUT1 and OUT2. Since a differential delay cell can react only on the difference of the input signals, the next differential delay cell in the ring rejects these common mode noise signals.
The delay of the differential delay cell 10 is proportional to a time constant determined at its outputs. The value of the time constant is defined by the product of the resistance at the output, and the total lumped capacitance at the output to ground. If the value of the resistors 18 and 19 could be changed, it would be possible to change the delay time of the differential delay cell 10, and thus force the ring-oscillator work at a controlled frequency.
A practical realization of this concept is shown in prior art FIG. 2. Differential delay cell 10 is essentially a fully differential amplifier stage loaded with symmetrical loads 22. The combination of NMOS transistor 23 and diode connected NMOS transistor 24 emulates the resistive load of FIG. 1, whose value can be controlled by voltage Vctrl present at the gate of NMOS transistor 23. A control circuit 21 adjusts the current of PMOS transistor 25 such that the upper limit of the voltage at the outputs OUT1 and OUT2 is equal to the control voltage Vctrl applied to the input of an amplitude control operational amplifier 28. The amplitude control operational amplifier 28 works in a negative feedback configuration with a replica of one-half of the differential delay cell 10, represented as delay cell 29. The delay of delay cell 29 is also controlled by Vctrl and is reversely proportional to it.
It is desirable to obtain higher frequencies from the ring oscillator. This can be achieved in the prior art differential delay cell by the way of reducing the effective load resistance of the differential delay cell either by keeping the same amplitude of oscillation and respectively increasing the current, or by reducing the amplitude of oscillation without substantial increase of the current. However, to be able to oscillate, the differential delay cell should have the product of the transconductance of the input PMOS transistors 26 or 27 and the effective load resistance to be substantially greater than 1. Both ways of achieving higher frequency, as described above, demand higher input transistor transconductance. To achieve higher input transistor transconductance in the prior art requires that the width of the input transistors have to be large. This substantially increases the load capacitance associated with the outputs OUT1 and OUT2 and leads either to slowing down the VCO or burning an additional current to reach the desired frequency.
Therefore it is desirable to have the amplitude of the output voltage of the differential delay cell to be independent of the control voltage controlling the delay, which will linearize the transfer characteristic of the VCO.
It is also desirable to provide a means to increase the sensitivity of the differential delay cell towards the change of the differential voltage at its inputs, and to further reduce the amplitude of the oscillation for a differential delay cell. This would reduce the transition time and increase the frequency of the oscillation for the same bias current and load capacitance.